Ion-implanted junction field effect transistors (hereinafter termed I.sup.2 JFETs) typically contain a buried (ion-implanted) channel region which bridges or joins respective source and drain regions of the JFET and the conductive properties of which are controlled by modulation of the space-charge region width formed with the adjoining top gate and bottom gate regions. Where the top gate has been formed of a single continuous layer, the resulting device is subject to drain-source punch-through at the (thin oxide) insulator interface with the top gate. The mechanism which gives rise to this punch-through effect differs for P- channel and N- channel JFETs.
More specifically, in a PJFET device (P-channel) the thin oxide layer overlying the surface of the device, and through which the top gate and conductive channel therebeneath are implanted, traps electrons (due to the presence of ion-implanted N-type impurities (e.g. phosphorous or arsenic) within oxide). Namely, the density of trapped electrons within the oxide is of sufficient concentration to cause the formation of a depletion region extending from source to drain, or even an inversion region, in the N-type gate surface layer at the oxide interface. For a discussion of this phenomenon, attention may be directed to a book entitled "MOS Physics and Technology" by E.H. Nicollian and J.R. Brews, Wiley, New York, 1982, Chapter 11, pp. 548-549.
In an NJFET (N-channel device), the surface depletion of the top gate (P-type) is principally caused by segregation of P-type impurities (e.g. boron) which, in the worst case, will overcome any beneficial effect of implanted phosphorous-induced electron-trapping. In addition, NJFETs are more likely to undergo surface inversion due to gamma radiation-induced fixed positive oxide charge.
To counter or overcome the drain-source punch-through effect, a high concentration region, which effectively acts as a barrier to drain-source punch-through may be formed in the top gate layer. The provision of such a region is described in my earlier filed patent entitled "Technique for Increasing Gate Drain Breakdown Voltage of Ion-Implanted JFET" issued Jul. 28, 1987, U.S. Pat. No. 4,683,485 and assigned to the Assignee of the present application.
As described in that patent, a high impurity concentration region of the same conductivity type as the top gate results in an impurity distribution profile at the surface of the device, which effectively makes up for the lack of charge carriers available from the top gate when the device is biased near pinch-off, thereby preventing the top gate structure from being fully depleted of charge carriers.
As the operational frequencies at which linear devices, such as the above described JFET continue to increase, dimensional tolerances of the device geometries become more critical. Where the JFET source-drain separation is reduced to a distance on the order of 7 to 8 microns, it becomes very difficult to form the high impurity concentration channel barrier region within the top gate without degrading the drain/source breakdown voltage which must be maintained in the range of 20V-40V. In other words, precise alignment of the high impurity concentration barrier region with the very closely spaced source and the drain is a critical requirement in shallow channel applications.